The invention relates to bus bridges. More particularly, the invention relates to a bus bridge designed to connect a Peripheral Component Interface (PCI) bus or a PCI Extended (PCI-X) bus to another bus of any type. The PCI bus standard is found in Peripheral Component Interconnect (PCI) Local Bus Specification, Rev. 2.2, Dec. 18, 1998, available from the PCI Special Interest Group, Portland, Oreg. The PCI-X bus standard, a high-speed addendum to the PCI standard, is found in PCI-X Specification, Rev. 1.0a, Jul. 24, 2000, also available from the PCI Special Interest Group.
To support the high-bandwidth data transfers demanded by modern applications, data are clocked across the buses of today""s computer/digital systems at tremendous rates. To achieve reliable, high-speed data transfer, such systems often include a number of buses arranged in hierarchy and interconnected by devices called bus bridges.
A bus bridge is basically a load-isolating device that allows multiple devices to appear as a single capacitive load to a bus. Although the reduced capacitive loading increases the maximum frequency at which a bus can be operated, the bridge adds a layer of complexity to the design and operation of the computer/digital system. Further complexity can result if the bridge is used to interconnect different types of buses because the bridge will translate data, commands, and other control signals between the two bus formats.
The PCI to PCI Bridge Architecture Specification, Dec. 18, 1998, available from the PCI Special Interest Group, defines ordering rules for a PCI bridge. The ordering rules define the situations in which a request on the bridge may or may not pass a prior request on the bridge. These rules are necessary in order to avoid system deadlocks or the use of stale data.
Current PCI bridges rely on complex schemes that augment a set of first-in-first-out (FIFO) and/or random access structures with request numbering or other token-based schemes. Additional logic must then monitor the tokens to determine which requests may proceed and which requests must wait in accordance with the PCI Bridge ordering rules.